Operation (Intellivision)

the general expected operation of each main component/ic is detailed below stic (u4) the stic is the standard television interface chip it controls the reset of the rest of the system, drives the video output signals to the video circuit and more first check the stic has all the voltage rails required 5 7v pin 20 this comes from the flying lead 5 7v power off the main power board, and this powers only this chip the clock (pin 15) should be a 4mhz sinewave about 3 4v if the clock is lower, it is sometimes ok, but mostly a problem for example, some boards have a 2v peak to peak and work on, but other times that can prevent boot this is the main clock that starts all of the system, as the stic runs off this clock to generate the phase 1/2 signals, so you want this to be a strong 3 4v during reset sr3 (pin 2) should also pulse for a period, usually 40us pulses lasting around 10ms, but this can vary a lot the important thing is you get some activity when out of reset the stic knows when there is a game present because the cartridge loops the bc1 (pin 32 / 42), bc2 (pin 32 / 40) and bdir (pin 36 / 38) pins together to rule out game issues (actual data corruption) or if you don't have a game, you can just loop these pins and the system should boot (and you should see activity on the bc1 / bc2 / bdir pins on an oscilloscope) you will typically boot to a red boot screen the stic bc1 (pin 7), bc2 (pin 6) and bdir (pin 8) go to the cartridge bc1 (pin 32), bc2 (pin 34) and bdir (pin 36) the loop basically joins the stic pins to the bc1 (pin 42), bc2 (pin 40) and bdir (pin 38) this allows the cpu to control the stic as the pins 38 / 40 / 42 are outputs from the cpu through the quad xor u17 2 on reset (press the reset button) you should see the bc1 (pin 7), bc2 (pin 6) and bdir (pin 8) pins have brief activity as it tries to read a game this is typically just a few high pulses for around 100ms if you do not ? !dtb (pin 4) and !bar (pin 5) sometimes toggle for around 15ms when resetting without a game sr1 (pin 9) should always output a 50/60hz signal so long as !reset (pin 14) is high when there is no game the high and low period are both large when the game has loaded, there is a 99% high period and a short low pulse o1 (pin 10) and o2 (pin 11) should both be 5v 2mhz square wave signal reset signal the main reset signal of the system is the reset button which directly sinks the stic !reset (pin 14) low to reset the stic the cartridge can also reset the stic by changing from a high to low signal on its !reset (pin 12) the cartridge generally leaves the !reset pin low, and brings it high then low again to trigger a reset note the cartridge !reset is passed through a non polorized capacitor so the 5v of the cartridge and the 5 7v of the stic do not mix as it is capacitively coupled, the signal from the cartridge has to go from a 5v to a 0v to trigger a small pulse low on the stic it cannot keep the stic is reset due to the capacitor cpu (u1) first check the cpu has all the voltage rails required 5v pin 28 / 32 / 33 / 34 / 40 12v pin 36 3v pin 35 next, check the !msync (pin 2) signal is 5 7v this is the out of reset signal the !msync is pulled high, and sunk low by the stic if it is in reset this means if there is no game, the stic is not activated so the !msync is always high unless the reset button is held with a game in, the stic activates, and if it fines a problem it will hold !msync low in reset always , the following pins pins 37 / 38 should be 2mhz square wave 11v !msync (pin 2) should be 5 7v (might need to press reset a few times) !intr (pin 28) is 4 5v (it is pulled to 5v) ebc1 (pin 1) should be 5v tc1 (pin 26) should be low halt (pin 30) should be low !stpst (pin 32) should be 5v bdady (pin 33) should be 5v !pcit (pin 40) should be 4 5v without a game in dx (pins 6 to 21) should be tri state (1 7v approx floating) bc1 (pin 3), bc2 (pin 4) and bdir (pin 5) should be low !intrm (pin 27) is 5 5v pulsing low for 66% every 50/60hz this signal is driven from the stic (u4) on the sr1 pin if dc high, reset a few times ebcax (pins 22 / 23 / 24 / 25) should be 5v !busack (pin 29) should be 4 8v !busreq (pin 31) should be 5 4v with a game in dx (pins 6 to 21) should be toggling 5v bc1 (pin 3), bc2 (pin 4) and bdir (pin 5) should be toggling 5v !intrm (pin 27) is 5 5v pulsing low for 7 35us every 50/60hz this signal is driven from the stic (u4) on the sr1 pin if dc high, reset a few times ebcax (pins 22 / 23 / 24 / 25) should be toggling 5v !busack (pin 29) should be toggling 4 8v !busreq (pin 31) should be toggling 5 4v system ram (u2) first check the ra 3 9600 system ram has all the voltage rails required 5v pin 9 12v pin 10 3v pin 11 make sure you have a 2mhz 11v square wave on pin 8 exec 9504 (u3) first check the exec 9504 has all the voltage rails required 5v pin 1 (schematic is wrong, says pin 28) the exec 9504 is controlled by the bc1, bc2 and bdir pins which are driven by the game cartridge initially the exec 9404 will not do anything until bdir goes high and bc1 and bc2 are low this is the bar signal after this is listens for all subsequent combinations of bdir, bc1 and bc2 combinations when bdir is low and both bc1 and bc2 go high (read), the data bus db10 to db15 are pulled low, and the 10 bit data pushed out onto db0 to db9 exec 9502 (u9) the exec 9502 is the program rom acting as program memory for the cp1610 cpu first check the exec 9502 has all the voltage rails required 5v pin 1 the exec 9502 is activated by the !msync (pin 20) going high if !msync is low the chip is held in reset the !msync is pulled high, and sunk low if you press the reset button it then waits for bc2 to go high while bc1 and bdir are low (iab) which are driven by the game cartridge once it receives this it outputs the starting address onto the data bus dbx pins operation then continues following based on the input control signals graphics rom (u5) the graphics rom will have its address and data pins briefly pulsed as a game is being loaded if there is no game or it fails, these pins will idle at 0v right after reset if a game successfully loads, the address and data pins continue to toggle and the !intrm pin duty cycle reduces from 12ms to 35us always , the following pins !rw (pin 40) is 4v dc !msync (pin 16) is 5 4v dc without a game in !intrm (pin 2) is 5 5v pulsing low for 66% every 50/60hz this signal is driven from the stic (u4) on the sr1 pin if dc high, reset a few times !busack (pin 3) is 4 8v dc !en (pin 39) is 3 6v dc !dws (pin 38) is 0 4v dc !dtb (pin 37) is 0 4v dc !bar (pin 36) is 0 4v dc ax pins are 0v ydx pins are 0v sdx pins are 0v with a game in !intrm (pin 2) is 5 5v pulsing low for 7 35us every 50/60hz this signal is driven from the stic (u4) on the sr1 pin if dc high, reset a few times !busack (pin 3) is 4 8v toggling low !en (pin 39) is 3 6v pulsing low !dws (pin 38) is 5 6v pulsing high for around 7ms every 50/60hz !dtb (pin 37) is 5 6v pulsing !bar (pin 36) is 5 6v pulsing ax pins are pulsing 4 5v ydx pins are pulsing 4 5v sdx pins are pulsing 4 5v