The general expected operation of each main component/IC is detailed below.

The STIC is the Standard Television Interface Chip. It controls the reset of the rest of the system, drives the video output signals to the video circuit and more.

First check the STIC has all the voltage rails required:

This comes from the flying lead 5.7V power off the main power board, and this powers only this chip.

The clock (pin 15) should be a 4MHz sinewave about 3.4V.

During reset SR3 (pin 2) should also pulse for a period, usually 40us pulses lasting around 10ms, but this can vary a lot. The important thing is you get some activity when out of reset.

The STIC knows when there is a game present because the cartridge loops the BC1 (pin 32 / 42), BC2 (pin 32 / 40) and BDIR (pin 36 / 38) pins together.

To rule out game issues (actual data corruption) or if you don't have a game, you can just loop these pins and the system should boot (and you should see activity on the BC1 / BC2 / BDIR pins on an oscilloscope). You will typically boot to a red boot screen.

The STIC BC1 (pin 7), BC2 (pin 6) and BDIR (pin 8) go to the cartridge BC1 (pin 32), BC2 (pin 34) and BDIR (pin 36). The loop basically joins the STIC pins to the BC1 (pin 42), BC2 (pin 40) and BDIR (pin 38). This allows the CPU to control the STIC as the pins 38 / 40 / 42 are outputs from the CPU through the Quad XOR U17.2

On reset (press the reset button) you should see the BC1 (pin 7), BC2 (pin 6) and BDIR (pin 8) pins have brief activity as it tries to read a game. This is typically just a few high pulses for around 100ms.

!DTB (pin 4) and !BAR (pin 5) sometimes toggle for around 15ms when resetting without a game.

SR1 (pin 9) should always output a 50/60Hz signal so long as !RESET (pin 14) is high. When there is no game the high and low period are both large.

When the game has loaded, there is a 99% high period and a short low pulse.

O1 (pin 10) and O2 (pin 11) should both be 5V 2MHz square wave signal.

The main reset signal of the system is the reset button which directly sinks the STIC !RESET (pin 14) low to reset the STIC.

The cartridge can also reset the STIC by changing from a high to low signal on its !RESET (pin 12).

The cartridge generally leaves the !RESET pin low, and brings it high then low again to trigger a reset.

First check the CPU has all the voltage rails required:

Next, check the !MSYNC (pin 2) signal is 5.7V. This is the out-of-reset signal.

Always, the following pins:

Without a game in:

With a game in:

First check the RA-3-9600 System RAM has all the voltage rails required:

Make sure you have a 2MHz 11V square wave on pin 8.

First check the Exec 9504 has all the voltage rails required:

The Exec 9504 is controlled by the BC1, BC2 and BDIR pins which are driven by the game cartridge.

Initially the Exec 9404 will not do anything until BDIR goes high and BC1 and BC2 are low. This is the BAR signal.

After this is listens for all subsequent combinations of BDIR, BC1 and BC2 combinations.

When BDIR is low and both BC1 and BC2 go high (READ), the data bus DB10 to DB15 are pulled low, and the 10-bit data pushed out onto DB0 to DB9.

The Exec 9502 is the Program ROM acting as program memory for the CP1610 CPU.

First check the Exec 9502 has all the voltage rails required:

The Exec 9502 is activated by the !MSYNC (pin 20) going high. If !MSYNC is low the chip is held in reset.

It then waits for BC2 to go high while BC1 and BDIR are low (IAB) which are driven by the game cartridge.

Once it receives this it outputs the starting address onto the data bus DBx pins.

Operation then continues following based on the input control signals.

The Graphics ROM will have its address and data pins briefly pulsed as a game is being loaded. If there is no game or it fails, these pins will idle at 0V right after reset.

If a game successfully loads, the address and data pins continue to toggle and the !INTRM pin duty cycle reduces from 12ms to 35us.

Always, the following pins:

Without a game in:

With a game in: