System Clocks (Neo Geo AES)

the neo d0 is responsible for generating all system clocks firstly the 24mhz clock passes through a hex inverter, with its input also phase shifted to fall inline with the chroma clock, via cx23065), and then output into the neo d0 xin (pin 19), which then drives the neo d0 to generate all other clocks phase comparator circuit the chroma crystal gets synchronized to the 24mhz system clock via a phase comparator circuit cx23065 if this circuit is faulty, and you had not done the checkerboard fix, you would visually see a scrolling checkerboard interreference on the av output, instead of a static one this circuit is needed to keep everything on the composite color circuit in sync with the rest of the circuit although not critical and it would work without it, it is ideal to be working the circuit involves the crystals (3 579mhz for pal / 4 433mhz for ntsc, and the 24mhz) to be operational, as well as the passive components and the 74hc04 hex inverter, cx23065 and all passives to be working and connected chroma crystal (divi) generation the journey begins with the chroma crystal self oscillating circuit this generates the chroma crystal pulses onto the divi pin, which is fed into the cxa video encoder (for chroma output onto composite) and the lspc pin 143 (for locking the 24mhz clock in sync with it, to output on divo pin 131) divo / ref output the journey starts with the lspc chip outputting divo and ref pulses, and then it having divi input from the phase comparator firstly the divo and ref pins drives the cx23065 phase comparator located usually near the controller ports by neo d0 the divo out of the lspc drives the cx23065a input rin (pin 7) this is a 3 154 khz (or 933 khz i have observed) signal the other input vin (pin 6) is driven by the ref pin which is a 3 933 khz signal after this the cxa23065 will output on the amp out and in (pins 1 and 2) pulsing signal that reduces in amplitude, inverts, then stabilizes as it self balances out to a flat line after a few seconds this out signal goes through an 8 2k (or 10k, or 22k on some revision) resistor, often right below the cx23065 chip, then 100k resistor the 100k resistor will show a smooth dc signal that slowly rises as the pulses on the amp in and out settle, and on the output side of the 100k resistor (going to the 24mhz clock and hex inverter) it shows the 24mhz clock signal that is generated from the clock circuit this link between the phase comparator and the 24mhz clock is what feeds the phase detect out (pin 3) back into the amp out/in circuit to shift the 24mhz clock into phase with the ref/divo signals coming from the lspc the divi comes from the chroma crystal self oscillator circuit which feeds into the lspc then the lspc outputs the divo locked to that clock, which influences the 24mhz circuit as described above, based on divo the hex inverter (to the right of the cx23065 usually) receives this clock pulse on pin 1 the 24mhz signal is generated separately and fed into the cx23065 chip through the 100k and 22k resistors, and the amp out/in network even though the amp out (pin 1) of the cx23065 chip is out and looks like it drives the 24mhz circuit, it is the other way around if the 24mhz signal is not coming into the amp in (pin 2) then the cx23065 out (pin 3) will be 0v or sporadic confirm you have the 24mhz signal coming in to the 100k resistor and continuity from there all the way through to pin 1/2 of the cx23065 neo d0 clocks the final output on pin 4 of the hex inverter is a slightly square waveform 24mhz signal instead of sine, and goes to the neo d0 to feed it with xin (pin 19), which then generates every other clock for the rest of the system