Fat Agnus (Amiga 500)
The Fat Agnus chip (Address Generator Units) controls the address / memory registers and access and outputs video signals.
The Agnus also contains the blitter and copper co-processors.
The blitter is handles copying chip memory to chip memory faster than using the 68k. It can also do basic logic such as logical combining of up to 3 sources, pixel-precision shifting, line drawing and simple area filling.
During normal operation, below is a basic description of how every single pin should be operating if probing using an oscilloscope.
These tests are done in the minimum boot configuration (so with RAM, CIA, Paula and Denise removed).
- RGA pulsing
- 28MHz is 28MHz
- 14Mhz is 14Mhz
- 7MHz, !CDAC (!CLKEN) is 7MHz
- CCK, CCKQ is 3.54MHz
- DRA pulsing
- !LDS, !UDS, !RAS0, !RAS1, !CASU, !CASL pulsing
- A (except 19,20) pulse during load, most continue to pulse
- A19, A20 high
- !LPEN floating (from odd CIA)
- !VSYNC, !CSYNC, !HSYNC always present
- RD 2V
- !RESET 4.4-5V
- !INT 4.1V
- DMAL floating (from PAULA)
- !BLISS pulse during boot, then high at green screen
- !BLIT pulsing
- !WE 5V
- RW pulsing
- !REGEN pulse during boot, then high at green screen
- !AS pulsing
- !RAMEN 5V
CSYNC pin goes to U41 pins 8 and 9, which output then to pin 11 (going to HY1) and 12 (going through RP403 47R to JP11 to output AV port).
