Z80 Data Sharing (Sega Mega-Tech)

the two z80s, one from the sms and one from the mega drive, communicate with each other through a few buffers (ic13, ic15, ic33, ic34) and the glue logic (315 5347 and 315 5348) to join the address pins, data pins and control pins together when needed from each specific z80 data pins any 8 bit data that needs sharing between the sms and mega drive is done via the 74ls245 buffer ( ic13 ) located above the sms z80 the sms data pins are connected to port a , and the mega drive z80 data pins are connected to port b to test the data is coming through ok trigger on the z80 mega drive reset (pin 26), capture at 100us per division and capture all 8 data pins they should look very similar to the z80 mega drive data pins only slightly less noisy but the data is the same the !oe pin is controlled by the 315 5348 (pin 16), and should be low during reset the dir pin is controlled by the output of 74ls32 or gate ( ic21 pin 11 ) and should pulse constant during reset the 2 inputs to the or gate are sms z80 !red (pin 21) going to the input pin 12, and 315 5346 (pin 18) going to input pin 13 the data shoud look like this with golden axe at 100us per division note this is from the b side (meg adrive) which has higher peaks and a bit noisier, but the data will look very similar on the sms side just without the overshoots address pins the mega drive z80 (ic56) and its ram mb8464 (ic44) address pins go through bus translators 74ls245n ( ic33 / ic34 ) on the b side the a side connects to the address pins of the sms z80 (ic17), bios (ic20) and both ram chips hm65256blp 10 (ic28) and mb8464a (ic27) dir (pin 1) is to vcc so always high, meaning the master system address pins will pass through to the mega drive , so long as the !oe (pin 19) is low the !oe (pin 19) is controlled by the 315 5348 (pin 16) and should be low during the reset high period we see this during the out of reset stage one, when the master system brings the mega drives z80 and 68k out of reset , at the same time as enabling the bus transceiver so the sms can control the mega drives z80/68k the blue is the !reset of the z80 on the mega drive side, and the red is the !oe of the bus translators ic33/34 observe the address pins on the sms z80 during the initial out of reset stage to make sure all signals get getting to the mega drive z80 from the sms z80 without bad traces or corruption observe the opposite side of the connection by probing the same address pins but on the mega drive z80 the difference should be the sms z80 (port a) will have constant activity on the address lines both before and after the reset is high whereas the mega drive z80 should only have a ctivity during the high pulse of the reset signal all address pins look the same (all full data) like below, with a few exceptions the only notable pins are a7, a8 and a9 a s shown previously to have visible gaps in the pulses, and a14 is low the entire reset time control pins the z80 control pins are as follows on each z80 !mreq pin 19 !ioreq pin 20 !read pin 21 !write pin 22 m1 pin 27 these pins from the sms and mega drive are shared via the 74ls245 buffer ( ic15 ) located to the right of the sms z80 the sms control pins are connected to port a , and the mega drive z80 control pins are connected to port b note there is also an out of place pin setup on pins a6 > b6 where it isn't master system to mega drive pins, but 315 5308 !zwait pin 47 on port a going to the sms z80 !wait pin 24 on port b this means when the mega drive z80 is being controlled, the 315 5308 puts the sms z80 into wait the dir pin is tied to vcc the !oe pin is controlled by the 315 5346 above it (pin 18) and should be constantly pulsing during the reset high on the sms side (port a) !read is pulsing constantly !write is pulsing constantly !mreq is pulsing constantly !ioreq is held high m1 is pulsing constantly on the mega drive side (port b) !read is pulsing constantly during reset high !write is pulsed once low very briefly then held high !mreq is pulsing constantly during reset high !ioreq is held high m1 is pulsed once low very briefly then held high notice the key difference is the mega drives !write and m1 are basically high not pulsing finally, the port a !zwait (going to the 315 5308) and port b z80 !wait (going to sms z80 wait pin 24) is pulsing constantly during reset high