Video RAM (Neo Geo CDZ)
The main part of the Video data that is generated in the BIOS screen (the game and loading screens are different video overlays), is done by the video RAM and NEO-GRC chip. The NEO-GRC has 4 RAM that store video data.
The data comes through NEO-BUF chips to the left, and also involves the NEO-SFT near the center and DRAM on the far tight.
A mostly complete pinout is here.
NOTE: The following pins are not labelled:
- Pin 186 = RAM6/7 !OE (through 150R resistor B15
The RAM6 and 7 are 32k x 8bit CMOS RAM (CXK58257AM-70L).
- All RAM7 data pins go through 150R resistors to the NEO-GRC V6Dx pins
- All RAM6 data pins go through 150R resistors to the NEO-GRC V5Dx pins
- All address pins go through 150R resistors to the NEO-GRC VAx pins
- Both !WE go through 150R resistors to the NEO-GRC !WE (pin 185)
- Both !OE go through 150R resistors to the NEO-GRC !OE (pin 186)
- Both !CE go to GND
The RAM4 and 5 are 8k x 8bit CMOS RAM (CXK5864CM-70LL).
- Both CE2 go to VCC (5V)
- Both !CE1 go to GND
- Both !OE go to GND
- Both !WE go to the NEO-MGA-T (pin 174)
- Both A12 go to NEO-MGA-T (pin 175)
- Both A0 - A11 pins go through 150R resistors to the NEO-GRC PAx pins
- All RAM5 data pins go to the GA8 NEO-BUF (pins B8 - B15)
- All RAM4 data pins go to the GA8 NEO-BUF (pins B0 - B7)
The NEO-SFT to the center, and the D-RAM to the right side are also involved in generating the DRAM.
TheNEO-SFT and DRAM connect together, and the NEO-SFT connects to the NEO-BUF chips which ultimately join back to the NEO-GRC and Video RAM.
