Mega Drive Circuit (Sega Mega-Tech)

here are some useful pin diagrams and details for checking parts of the mega drive system 315 5313 (vdp) the 315 5313 is the main video display processor the vd0 vd15 (pins 55 to 70) are the 68k data pins the va1 va23 (pins 71 to 93) are the 68k address pins the !br (pin 99) is an output from the 315 5313 that when low indicates it has become the bus master this pin goes to the 315 5347 (pin 4) to let it know the 315 5347 (pin 19) goes to the 68k input !br (pin 13) this pulses once every frame this signal is only present when the game has loaded !bgack (pin 100) is an output sent to the 315 5348 the 315 5313 pin goes to 315 5348 (pin 17) the signal should be sent low to state the 315 5313 wants to be the bus master when it is high, the 315 5313 is not operating the address/data bus remember, if !br is high this pin is ignored as it is tied to multiple devices and if !br is high it isn't the 315 5313 that is requesting control, so the pin signals are being driven by another device !bg (pin 101) is an input to the 315 5313 that comes from the 68k the 315 5313 pin goes to 315 5348 (pin 19) the 68k pin goes to 315 5348 (pin 2) the signal should have a few pulses at the start of every frame this signal is only present when the game has loaded sel1 (pin 48) is the 68k clock i/o control it should always be low vclk (pin 49) is the 68k clock and should be 7 67mhz signal 315 5308 315 5309 the 315 5309 is responsible for handling the user controller ports, extension port and the version register (language, region) 68k cpu the 68k is used to process and read in the game data and run the game !bgack (pin 12) is controlled through various logic signals going into the 315 5348 the 68k pin goes to 315 5348 (pin 4) the signal should be high to allow the 68k to operate (stating no other bus master is controlling the line) z80 cpu the !zint (pin 16) is an input coming from the output of 315 5313 !zint (pin 98) that pulses low once every frame (so 50 or 60hz) video ram ad0 ad7 (pins 31 to 38) are the vram address/data pins sd0 sd7 (pins 1 to 8) are the vram data pins !se0, !sc, !ras1, !cas1, !we0, !oe1 (pins 9 to 16) are all stroke control for the vram all these pins go directly to the two vram chips (mb81461) clock generator (315 5345) the custom sega ic 315 5345 is responsible of edclk generation (external dot clock in h40 mode, based on hsync and mclk inputs) and 68k ram refresh it has a factory fit 1 2k resistor between !hsync (pin 2) and vcc (pin 16) to keep !hsync high until sunk low reset signals the 315 5313, 315 5309 and 315 5308 have a lot of the systems reset signals !wres (hard reset) input into 315 5308 high to keep out of reset, low to reset shorted to vcc directly so never in reset !sres connected to both the 315 5308 and 315 5309 the 315 5313 is the driver that outputs this signal to control the reset of the 315 5308 and 315 5309 the 315 5308 and 315 5309 have this pin pulled high so it is out of reset by default, but sunk low by the 315 5313 as needed the 68k is also controlled by the 315 5308 which follows the same reset pattern as the !sres !vres (68k reset) open collector output on 68k high to keep out of reset, low to reset can be sunk low to reset 68k, or the 68k can reset itself if via a software reset the 315 5308 controls this pin !mres (cartridge reset) on mega drive this allows games to send the !mres low on mega tech it is driven to the cartridge instead, by output pin 18 of ic52 buffer, with the input pin 2 being connected to !sres of 315 5308 so ultimately the cartridge is out of reset so long as the 315 logics are !fres (expansion port reset) not connected on mega tech, pin is 315 5309 pin 10 !zreset (z80 reset) the mega drives z80 reset is controlled by the 315 5308 on pin 45 rgb output r, g and b (pins 27, 28, 29) are the rgb analog outputs these go to resistors/transistors/caps down by rgb1 before coming out of the rgb1 connector !csync (pin 42) goes into a 74ls125 buffer (ic69 pin 9 input) above the rgb1 connector the output pin 10 goes to the rgb1 connector pin 4 video signals !vsync (pin 41) and !hsync (pin 43) should be valid 5v logic vsync/hsync signals !pal (pin 46) is high for 60hz, low for 50hz clocks edclk (pin 53) is the dot clock (13 42mhz or 10 7mhz) mclk (pin 52) is the master clock (53 7mhz) zclk (pin 51) is the z80 clock (3 58mhz) sbcr (pin 50) is the chroma sub carrier clock (3 58mhz or 4 43mhz) vclk (pin 49) is the 68k clock and should be 7 67mhz signal auxiliary signals !m3/sel0 is meant to be the cpu select pin (selecting between 68k or z80) observing working consoles i've never seen it do anything except be logic high trace checks if you would like to start by checking the main 68k/z80/ram and 315 logic traces have good continuity, here is a trace map