Mega Drive Circuit (Sega Mega-Tech)
Here are some useful pin diagrams and details for checking parts of the Mega Drive System
The 315-5313 is the main Video Display Processor.
The VD0-VD15 (pins 55 to 70) are the 68k Data pins.
The VA1-VA23 (pins 71 to 93) are the 68k Address pins.
The !BR (pin 99) is an output from the 315-5313 that when low indicates it has become the bus master. This pin goes to the 315-5347 (pin 4) to let it know. The 315-5347 (pin 19) goes to the 68k input !BR (pin 13). This pulses once every frame. This signal is only present when the game has loaded.
!BGACK (pin 100) is an output sent to the 315-5348. The 315-5313 pin goes to 315-5348 (pin 17). The signal should be sent low to state the 315-5313 wants to be the bus master. When it is high, the 315-5313 is not operating the address/data bus.
Remember, if !BR is high this pin is ignored as it is tied to multiple devices and if !BR is high it isn't the 315-5313 that is requesting control, so the pin signals are being driven by another device.
!BG (pin 101) is an input to the 315-5313 that comes from the 68k. The 315-5313 pin goes to 315-5348 (pin 19). The 68k pin goes to 315-5348 (pin 2).The signal should have a few pulses at the start of every frame. This signal is only present when the game has loaded.
SEL1 (pin 48) is the 68K clock I/O control. It should always be low.
VCLK (pin 49) is the 68k clock and should be 7.67MHz signal.
The 315-5309 is responsible for handling the user controller ports, extension port and the version register (language, region).
The 68k is used to process and read in the game data and run the game.
!BGACK (pin 12) is controlled through various logic signals going into the 315-5348. The 68k pin goes to 315-5348 (pin 4). The signal should be high to allow the 68k to operate (stating no other bus master is controlling the line).
The !ZINT (pin 16) is an input coming from the output of 315-5313 !ZINT (pin 98) that pulses low once every frame (so 50 or 60Hz).
AD0-AD7 (pins 31 to 38) are the VRAM Address/Data pins.
SD0-SD7 (pins 1 to 8) are the VRAM Data pins.
!SE0, !SC, !RAS1, !CAS1, !WE0, !OE1 (pins 9 to 16) are all stroke control for the VRAM.
All these pins go directly to the two VRAM chips (MB81461).
The custom Sega IC 315-5345 is responsible of EDCLK generation (external dot clock in H40 mode, based on HSYNC and MCLK inputs) and 68k RAM refresh.
It has a factory fit 1.2k resistor between !HSYNC (pin 2) and VCC (pin 16) to keep !HSYNC high until sunk low.
The 315-5313, 315-5309 and 315-5308 have a lot of the systems reset signals.
Input into 315-5308. High to keep out of reset, low to reset. Shorted to VCC directly so never in reset.
Connected to both the 315-5308 and 315-5309.
The 315-5313 is the driver that outputs this signal to control the reset of the 315-5308 and 315-5309.
The 315-5308 and 315-5309 have this pin pulled high so it is out of reset by default, but sunk low by the 315-5313 as needed.
The 68k is also controlled by the 315-5308 which follows the same reset pattern as the !SRES.
Open Collector output on 68k.
High to keep out of reset, low to reset
Can be sunk low to reset 68k, or the 68k can reset itself if via a software reset.
The 315-5308 controls this pin.
On Mega Drive this allows games to send the !MRES low. On Mega-Tech it is driven to the cartridge instead, by output pin 18 of IC52 Buffer, with the input pin 2 being connected to !SRES of 315-5308.
So ultimately the cartridge is out of reset so long as the 315 logics are.
Not connected on Mega-Tech, Pin is 315-5309 pin 10.
The Mega Drives Z80 reset is controlled by the 315-5308 on pin 45.
R, G and B (pins 27, 28, 29) are the RGB analog outputs.
These go to resistors/transistors/caps down by RGB1 before coming out of the RGB1 connector.
!CSYNC (pin 42) goes into a 74LS125 Buffer (IC69 pin 9 input) above the RGB1 connector.
The output pin 10 goes to the RGB1 connector pin 4.
!VSYNC (pin 41) and !HSYNC (pin 43) should be valid 5V logic VSYNC/HSYNC signals.
!PAL (pin 46) is high for 60Hz, low for 50Hz.
EDCLK (pin 53) is the Dot Clock (13.42MHz or 10.7MHz).
MCLK (pin 52) is the master clock (53.7MHz).
ZCLK (pin 51) is the Z80 clock (3.58MHz).
SBCR (pin 50) is the chroma sub-carrier clock (3.58MHz or 4.43MHz).
VCLK (pin 49) is the 68k clock and should be 7.67MHz signal.
!M3/SEL0 is meant to be the CPU select pin (selecting between 68k or Z80).
Observing working consoles I've never seen it do anything except be logic high.
If you would like to start by checking the main 68k/Z80/RAM and 315 logic traces have good continuity, here is a trace map.
īģŋ
