Mega Drive 68k (Sega Mega-Tech)

if you are suspecting issues with the mega drive system and want to check the 68k operation, this guide will take you through the expected behaviour and bring up make sure to have at least one game in the slot when doing any of these tests 68k operation start with the minimum required to see some activity on the 68k vcc must be 5v valid clk pulse !reset must be high (to come out of reset) !halt must be high (to not be halted) e signal output with this, you should see the e pin pulsing at 767khz this is a free running internal clock output so should be present regardless bus control then next thing to look for is that the 68k is being configured for the bus control, otherwise it will not attempt to do anything the following all need to be true to start the 68k toggling the address bus ip0 / ip1 / ip2 must be high (stating no interrupts) !berr must be high (stating no bus error) !br must be high (allowing bus control) !bgack must be high (indicating no other bus master) if all the above is true, you should see the address pins toggle at least for a cycle, as the 68k attempts by default to read data from the data bus note during the first out of reset when the sms reads the game headers, the 68k is disabled because the !bgack is sunk low, indicating there is another bus master out of reset when powering up, the 68k should be brought out of reset on pin 18 by the sms while it reads game titles, then back to low held in reset, and finally released again ready to load and play games the reset pin is controlled by the pla 315 5347 ic31 on pin 11 here is the typical reset cycle when the console is working note the initial short out of reset as game headers are loaded, then the permanent out of reset after you will also see the quick in and out of reset on the second rise this is typical when a game successfully loads clock the next thing to check is you have a valid 7 67mhz clock on pin 15 this clock should be there all the time regardless of reset or state of the system address strobe the !as pin 6 indicates to the 68k there is a valid address on the address bus 68k ram some basic checks that the two ram chips for the 68k are getting controlled right during the out of reset pulse is to monitor for the following vdd is 5v r/!w is 5v all address pins toggle constantly during out of reset !oe toggle constantly during out of reset !ce is 5v (this toggles once a game loads later on) note the tc51832 can be substituted with the hm65256blp traces here you can check for continuity between the 68k and its ram