LCD Circuit (Game Gear)
NOTE: Here are my quick notes to help people diagnose the issues with no contrast on the LCD. Check your backlight tube is lit firstly or use a torch from behind to see the screen if not.
The job of this circuit is to send pulsing differential paired signals ranging from around 8 to 18V to the LCDs TPR1/TPR2 and VSS/VDD pins (so two pairs of complimentary signals), whereby the higher the voltage the more the LCD crystals twist allowing more light through, and "turning on" the display.
0V to 5V
-8V to -18V
Same as VSS
Same as VSS
8V to 18V
Same as VDD
Same as VDD
1.4 to 2.6V
0V or 5V
Before jumping into diagnosing all points. its sometimes faster and worth testing some common points of corrosion that break parts of the LCD circuit due to the capacitor leakage. Below are some common points and what they restore.
Solder a wire from the top of C38 to the top of D2.
Solder a wire from the top of C37 to the left of C52.
This restores the following two paths.
Solder a wire from the top of C47 to the right of C60.
And this is the path it fixes.
With nothing in, or an SMS game in, GG pin is 5V (floating high).
With GG game in it pulls the pin low to ground.
R31 is the gate to Q5 which the only job is it gives R32 a path to ground lowering the output voltage range of the contrast wheel a little. So when a GG game is in, it turns off Q5 and the output voltage at the contrast wheel is a little higher Measuring top of R32: GG game = 19.3V SMS game = 16.6V
Contrast wheels job is to saturate the base of Q6 turning it on more as it changes resistance Measuring gate input of Q6 (so output of contrast wheel): GG game = 9.4V to 18.56V SMS game = 8V to 15.8V R35 output of Q6 is just current limiting, which then feeds Q8 with this approx 8-18V signal
R36/37 form a voltage divider which then drives Q7 base just like Q6, only now lower voltage range powered from 5V rail. The output of Q7 is then a voltage divider over R38/39/40 on the 5V rail giving a lower range matching Q6 but at about 1/3rd the voltage . This is the VD2 LCD pin. Measuring Q7 output (top of R39) - VD2 LCD pin GG game = 2.8V to 5V SMS game = 2.35V to 4.75V
Between R39 and ground is R40 which is another voltage divider just lower voltage still, generating the VM pin for the LCD. Measuring bottom of R40 - VD2 LCD pin GG game = 1.73V to 2.74V SMS game = 1.5V to 2.7V
A is a pulsing 5V signal going active high with a width of 188us and a 63us duty cycle.
Every 2 frames of VSYNC (every 33ms), the polarity changes to the signal becomes an active low instead of active high. Then 2 frames later it toggles back to an active high signal.
C54/C55 (C44/C45 on 1 ASIC) are pulsed outputs at the voltage level of R35 (8-18V) that match the 5V pulses of the A pin being driven by ASIC.
Coming off C55 (C45 on 1 ASIC), also joined to C54 (C44 on 1 ASIC) via a resistor R45) is the LCD pin VSS. This pin is controlled through Q10 and Q11 (via the A pin of the ASIC) to form the VSS final signal.
Coming off C54 is the LCD pin VDD. This pin is controlled through Q10 and Q11 (via the A pin of the ASIC) to form the VDD final signal.
The final VSS pin is a pulsing negative voltage ranging from -8 to -18V, pulsing in-sync with the A pin.
The final VDD pin is a pulsing positive voltage ranging from 8 to 18V, pulsing in-sync with the A pin.
Coming off the VSS pin is resistor R46 and capacitor C56 (C46 on 1 ASIC) in parallel, which then go to TPR2 pin. This pin, as it is joined to the VSS pin, is also controlled by the A pin of the ASIC.
Coming off the VDD pin is resistor R47 and capacitor C57 (C47 on 1 ASIC) in parallel, which then go to TPR1 pin. This pin, as it is joined to the VDD pin, is also controlled by the A pin of the ASIC.
TPR2 is identical to VSS pin except with a small slope added by the capacitor.
TPR1 is identical to VDD pin except with a small slope added by the capacitor.