Graphics Rendering (Neo Geo AES)

when you get issues with the neo geo not rendering correctly it is good to know how the screen generally renders the neo geo has various layers and graphics overlays a great site for much more technical details is https //wiki neogeodev org/ https //wiki neogeodev org/ fix layer the fix layer is a tile based layer, which supports transparency and always overlaps sprites the fix layer is non scrollable it is often used for text, huds, scores and health bars the tiles are 8x8 pixels they can be grouped into meta tiles of 16x16 and 32x32 the tiles are stored in the s rom (static rom) in some mvs systems, there is a dip32 ic labelled sfix (system fix) rom it is a 64kib or 128kib rom containing the default fix layer tileset loaded into s rom and used to display menus and text when no cartridge is inserted as well as the lspc handling the fix layer, the neo b1 handles the fix layer and reads in the fixdc pins from the cartridge slot directly sprites the sprites are all drawn below the fix layer this is for everything else including backgrounds, characters, objects, bullets, effects and anything else that is not on the fix layer sprites are stored in the c roms sprites are made of tiles (called characters) from the c roms on the cartridge tiles are always 16x16 pixels in size and can contain 15 colors (the color index 0 is used for transparency) when combined (fix + sprite layers) you end up with the final image l0 rom the l0 rom is a 64kib (or 128kib with a16 tied to ground) rom chip it is either a dip28 tc531000, a sop32 tc531001 or integrated into the neo grc2 (on m1vs and cdz for example) the l0 rom stores byte values used by lspc to shrink sprites vertically faults in the l0 rom lead to vertical stretching or shrinking issues pins / trace routes it is useful to understand where some of the data, address and control pins go to from the cartrige and how they relate to the graphics p bus pins the p bus (labelled pcx on schematic nets) is the c rom (sprites) and s rom (fix layer) addresses going between the cartridge slot and lspc, as well as several other places the p bus is a multiplexed address lane that has the c rom and s rom addresses and goes to the lspc px pins 68k address / data pins the address and data pins for the cartridge (labelled acx and dcx on the schematic nets) go to the 68k as well as the lspc ax and dx pins fix layer data pins the fix layer data pins from the cartrigde (labelled fixdcx on the schematic nets) go to the neo b1 which is the graphics processor for the fix layer lspc the lspc / lspc2 is the line sprite controller it is responsible for generating s rom, c rom and l0 rom addresses based on current display line and vram content as well as this is also generates sync output, talks to the neo b1, generates 68k irqs and handles 68k vram access arbitration the p bus, 68k data/address pins and many other pins from the cartridges all go to the lspc example layers here are a few more examples of the fix layer and sprite layers separated, and then the final image this is from metal slug x on the mvs and another one in game