ASIC Dead Test (Game Gear)

once you have red light boot, the next step is confirm your asic is running as expected out of reset with no game tldr; quick tests check 5v present on asic pins check xtal1 and xtal2 pins have 32 215mhz clock check samp pin has 16 11mhz check cclk 3 579mhz clock output and a vclk 10 74mhz clock asic 5v make sure your asic is receiving the 5v power from the system by measuring the 5v pins on the asic xtl2 25mhz driver the xtl2 pin of the asic is an internal oscillator that should output approximately 26mhz oscillations when there is no external 32 215mhz no external 32 215mhz crystal installed, even when not out of reset the only thing required for the xtl2 pin to start oscillating is on 2 asic models, both asics are functional and can communicate they talk to each other over the address and data pins on boot , and once they establish they are both present, the internal oscillation starts requirements for test 5v power present both asics present good connection between address and data pins this is a perfect one stop check for seeing if the asic is dead remove the 32 215mhz crystal and probe the xtl2 pin xlt1 should sit around 2 5v oscillating slightly (likely just the cross talk from the xtl2 pin typically if they asic pair cannot communicate , xtl2 stays at 5v , and xtl1 at 0v , and once they communicate the oscillation starts on pin xtl2 reflow all pins on both asics if you have issues, this often solves the issue if not, it is highly likely the asic is dead crystal 32 215mhz although incredibly rare, if the asic is not receiving a clock signal due to a faulty crystal or supporting components it will not do anything as it cannot run if you have an oscilloscope you can test the pads of the crystal for a 32 215mhz clock signal if not just inspect the area around the clock components for obvious damage there are 2 resistors and a crystal on one side of the board, and directly underneath are the 2 capacitors xtl1/xtl2 clock drivers the crystal on the asic along with its capacitors and resistors , plus the asic pins xtl1 and xtl2 must all be working in order to generate a valid 32 215mhz signal use an oscilloscope to check pin xtl1 and xtl2 both should have a 32 215mhz signal, with xtl1 being slightly lower in amplitude if you do not see these signals , check your resistors ( r13 = 3k , r14 = 200r on 2 asic, r24 = 1 8k , r25 = 50r on 1 asic) measure within spec and have their traces in tact connecting to the crystal pins and asic pins confirm your capacitors (c15/16 on 2 asic, c38/40 on 1 asic) do not measure continuity over their pins, and have good traces to the crystal pins and to ground if you want to remove them from circuit and test using an lcr meter they should measure 5pf to 22pf if all the above is good but you still have no clock, you have a bad asic or bad crystal to check if the asic is more than likely ok, sample the samp pin samp asic pin a good sign if the asic is alive is to check the samp pin using an oscilloscope if it is outputting a 16 11mhz signal then the asic is likely ok although this isn't guaranteed its a good check cclk / vclk clock pins the asic also generates a cclk 3 579mhz clock output and a vclk 10 74mhz clock output this is generated by the left asic on the 2 asic version if you do not see these signals, but all the tests above were ok, it is highly likely the asic is dead these clock signals do not need work ram, mpu or video ram to be output, only a valid vref/vres/vonof voltages and power out of reset if the asic receives the 5v and all vbat, vres and vonof, and those voltages are within range (vres/vonof greater than 0 6v and vres higher than vref) the asic should come out of reset measure the !reset pin to confirm it is 5v if !reset is 0v (still in reset), then typically this means you have a dead asic (confirm cclk, vclk for that), or shorts somewhere on the asic pins or passive components connected to some vital lines if you got a valid samp pin video signals the asic regardless of game or not, right after reset should start clocking out a valid vsync and hsync signal, as well as the alternative dw (vsync) and cl2 (hsync) signals we will use the dw and cl2 signals here dw vsync (pin 20 on lcd ribbon, pin 51 of ic3 on 2 asic, pin 50 on 1 asic) should look like this (a 16 7ms pulse width signal indicating the start of each frame of the image) cl2 hsync (pin 9 on lcd ribbon, pin 46 of ic3 on 2 asic, pin 55 on 1 asic) should look like this (a 63 8us pulse width signal indicating the start of each line of a single frame of the image) this confirms the asic is operational after this the asic should attempt to read the game file from the cartridge and with the assistance of the main ram start running the game code