68k Initial Boot (Macintosh SE/30)

after the glue logic chip brings all required pins on the 68k to their initial state the 68k should attempt to walk the bus and you will see constant address pins toggling as it loops over and over attempting a load the 68030 has a bi directional reset signal meaning it can both set the reset signal, and be reset by external sources luckily thanks to my deep dive reverse engineering the sega mega tech and the wiki articles on that i know how the 68k should come out of reset start with the minimum required to see some activity on the 68k vcc must be 5v valid clk pulse !reset must be high (to come out of reset) !halt must be high (to not be halted) here is a pinout from the underside bus control then next thing to look for is that the 68k is being configured for the bus control, otherwise it will not attempt to do anything the following all need to be true to start the 68k toggling the address bus ip0 / ip1 / ip2 must be high (stating no interrupts) !berr must be high (stating no bus error) !br must be high (allowing bus control) !bgack must be high (indicating no other bus master) if all the above is true, you should see the address pins toggle at least for a cycle, as the 68k attempts by default to read data from the data bus out of reset when powering up, the 68k should be brought out of reset by?? (to be determined) clock the next thing to check is you have a valid 15 67mhz clock on the clock pin this clock should be there all the time regardless of reset or state of the system address strobe the !as pin 6 indicates to the 68k there is a valid address on the address bus !berr when the 68030 attempts to access memory or an i/o device, it uses the address and data buses to communicate with the external chips and hardware if something goes wrong during this communication, such as a memory access error, a parity error, or a failure to receive a data acknowledge signal, a "bus error" is generated this !berr is then sent low by some other device (the one the 68030 attempted to read/write invalid address data to) and so it halts its execution and goes into an error handling state if you see !berr toggling low it is a sign something isn't happy with the data/address bus and something is invalid on the macintosh se/30 the following chips connect to !berr 68030 cpu (uk8) pal1644b (ui6) glue chip (ui8) pds header (j13) it is pulled up to 5v through the resistor pack rp7 so make sure that is connected and pulled high otherwise it would be constantly low this means that as the !berr is an input into the 68030, and the pds header is generally empty for initial boot attempts, the glue chip or the pal must be the ones driving the !berr low there is an open source jed file for the pal chip so if we figure out what pins are what inside the jed file we could understand exactly what happens on the !berr pin in the pal if it is an input, output or bi directional for how it's a mystery as soon as the system powers on, we typically see the address bus toggle, but only for a single pulse if there is a bus error from the glue/pal so if you see this then we have to solve that first before moving onto the 68k activity see this !berr issue here once i figure out the cause of this we can continue the documentation here \ d